The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
The gain of an MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility of the majority carrier in the transistor channel. The current carrying capability and hence the performance of an MOS transistor is proportional to the mobility of the majority carrier in the channel. The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor can be increased by applying a compressive longitudinal stress to the channel, especially when the transistor is fabricated on a silicon wafer with surface orientation (100) and the channel orientation coincides with the wafer crystallographic direction [011]. It is well known that a compressive longitudinal stress can be applied to a silicon MOS transistor by embedding a material such as silicon germanium (SiGe) at the ends of the transistor channel. Similarly, the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor can be increased by applying a tensile longitudinal stress to the channel. Such a stress can be applied to a silicon MOS transistor by embedding a material such as silicon doped with carbon at the ends of the transistor channel. Such methods, however, require the etching of trenches into the silicon substrate and the selective epitaxial deposition of silicon germanium and/or silicon carbon. A number of additional and difficult process steps are thus required to implement these know methods to achieve devices having stress enhanced carrier mobility.
Accordingly, it is desirable to provide stress enhanced mobility devices and methods for the fabrication of such devices that avoids the difficult process steps of the prior art. In addition, it especially is desirable to provide NMOS devices having stress enhanced mobility and to provide methods for fabricating NMOS devices having stress enhanced electron mobility. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.